Vic
Lets start at ground level
Extreme Tweaker
Ai Overclock Tuner: Manual
OC From Memory Level Up: Auto
FSB Frequency: 400
CPU Ratio Setting: 09.0
CPU Configuration
CPU Ratio Setting: 09.0
C1E Support: Disabled
CPU TM Function: Disabled
Max CPUID Value Limit: Disabled
Vanderpool Technology: Disabled
Execute Disable Bit: Disabled
Core Multi-Processing: Enabled
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: 333 (check memory speed, may need 400)
PCIE Frequency: 100
DRAM Frequency: 1600Mhz
DRAM Command Rate: 2N
DRAM Timing Control: Manual
1st Information: 7-7-7-20-6-82-6-3
CAS# Latency: 7
RAS# to CAS# Delay: 7
RAS# Pre Time: 7
RAS# ACT Time: 20
RAS# To RAS# Delay: 6
REF Cycle Time: 82
WRITE Recovery Time: 6
READ to Pre Time: 3
2nd Information : 9-4-5-4-6-4-6
READ to WRITE Delay (S/D): 9
WRITE to READ Delay (S): 4
WRITE to READ Delay (D): 5
READ to READ (S): 4
READ to READ (D): 6
WRITE to WRITE (S): 4
WRITE to WRITE (D): 6
3RD Information: 18-7-1-9-9
WRITE to PRE Delay: 18
READ to PRE Delay: 7
PRE to PRE Delay: 1
ALL PRE to ACT Delay: 9
ALL PRE to REF Delay: 9
DRAM Static Read Control: DISABLED
DRAM Dynamic Write Control: AUTO
DRAM Skew Control
DRAM CMD Skew on Channel A: Auto
DRAM CLK Skew on DIMM A1: Auto
DRAM CLK Skew on DIMM A2: Auto
DRAM CTL Skew on DIMM A1: Auto
DRAM CTL Skew on DIMM A2: Auto
DRAM CMD Skew on Channel B: Auto
DRAM CLK Skew on DIMM B1: Auto
DRAM CLK Skew on DIMM B2: Auto
DRAM CTL Skew on DIMM B1: Auto
DRAM CTL Skew on DIMM B2: Auto
Ai Clock Twister: Lighter
Ai Transaction Booster: Manual
Common Performance Level: 07
Pull-In of CHA PH1: Disabled
Pull-In of CHA PH2: Disabled
Pull-In of CHA PH3: Disabled
Pull-In of CHB PH1: Disabled
Pull-In of CHB PH2: Disabled
Pull-In of CHB PH3: Disabled
EPU II Phase Control: Auto
CPU Voltage: 1.28
Load-Line Calibration: Enabled
CPU PLL Voltage: 1.55
FSB Termination Voltage: 1.28
CPU GTLVerf (0): Auto
CPU GTLVerf (1): Auto
CPU GTLVerf (2): Auto
CPU GTLVerf (3): Auto
NB GTLVerf: Auto
North Bridge Voltage: 1.45
DRAM Voltage: 1.90
NB DDRVref: Auto
DDR3 ChannelA Vref: Auto
DDR3 ChannelB Vref: Auto
South Bridge 1.5 Voltage: 1.51106
South Bridge 1.05 Voltage: 1.06039
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
Advanced menu
North Bridge Chipset Configuration
Memory Remap Feature: Enabled
Run your tests and tell me if that is stable or not.
If it isn't stable then I suspect defective memory. If its not stable then run the latest MEMTEST
http://www.memtest.org/, 5 PASSES (take a bit of time) and see what test fails and how long it takes to fail.
If it is stable then the next step is to change COMMAND to 1T and retest.. if stable drop PL to 6 and test... if unstable in either, raise NB voltage to 1.52-1.55 and retest
1T and PL6 may not be possible.. you may be able to do 2T and PL 6
report back.. if you find a stable point we can go from there and expand on it